// **************************************************************
// COPYRIGHT(c)2016, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    :  
// Module name  :  
// Full name    :  
// Time         : 2016 
// Author       : Wang-Weina 
// Email        : 327422289@qq.com
// Data         : 
// Version      : V 1.0 
// 
// Abstract     :
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 2017.7.11\u66f4\u6539\u5185\u5bb9
// 1\u3001\u4e94\u8def\u5e27\u5206\u6790\u6a21\u5757\u7684\u8f93\u51fa\u7ed3\u679c\u4f9d\u9760\u8f6e\u8be2\u673a\u5236\u8f93\u51fa\uff0c\u53ef\u80fd\u51fa\u73b0\u7684\u95ee\u9898\u662f\uff1a\u6d41\u7684\u987a\u5e8f\u53ef\u80fd\u4f1a\u88ab\u6253\u4e71
//\u4e4b\u524d\u7684\u8f6e\u8be2\u673a\u5236\uff1apoll\u4fe1\u53f7\u75310\u81f34\u8df3\u53d8\uff0c\u5f53\u524d\u5e27\u5206\u6790\u6a21\u5757\u6709\u8f93\u51fa\u5219\u7acb\u523b\u8f93\u51fa\uff0c\u6ca1\u6709\u8f93\u51fa\u5219\u53ea\u80fd\u7b49\u5230\u4e0b\u4e00\u8f6e\u8f93\u51fa
//\u66f4\u6539\u540e
//\u8f6e\u8be2\u5230\u5f53\u524d\u652f\u8def\uff0c\u5982\u679c\u6ca1\u6709\u8f93\u51fa\u5219\u7b49\u5f85\uff0c\u5982\u679c\u6709\u8f93\u51fa\u5219\u8f93\u51fa
// *****************************************************************

// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// INFORMATION
// *******************

//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
//*******************
module pkt_analysis_top(
    input wire clk,
    input wire rst_n,
    input wire [ 9:0]ram_2p_cfg_register,
    input wire[255:0] pkt_data_i,
    input wire pkt_sop_i,
    input wire pkt_eop_i,
    input wire pkt_dval_i,
    input wire[4:0] pkt_mod_i,
    input wire[1:0] pkt_mod_ctl,

    // output reg[155:0] pkt2bv1,
    // output reg[147:0] pkt2bv2,
    // output reg[148:0] pkt2rbve,
    output reg[0:1023]match_field,
    //output reg[209:0] pkt_info,
    output reg[8:0] layend,
    //output reg info_dval
    output reg analyser_is_done_o,
    //output reg pkt_analyser_error_o,
    output wire analyser_is_working_o
    );

//*******************
//DEFINE LOCAL PARAMETER
//*******************
//parameter(s)

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
    
reg[2:0] poll;

//reg[209:0] pkt2class0_r,pkt2class1_r;
// wire [155:0] pkt2bv1_0,pkt2bv1_1;
// wire [147:0] pkt2bv2_0,pkt2bv2_1;
// wire [148:0] pkt2rbve_0,pkt2rbve_1;

// reg  [155:0] pkt2bv1_0_r,pkt2bv1_1_r;
// reg  [147:0] pkt2bv2_0_r,pkt2bv2_1_r;
// reg  [148:0] pkt2rbve_0_r,pkt2rbve_1_r;

reg[8:0] layend0_r,layend1_r,layend2_r,layend3_r,layend4_r;
reg analyser_is_done_r0,analyser_is_done_r1,analyser_is_done_r2,analyser_is_done_r3,analyser_is_done_r4;

//WIRES
(*mark_debug = "true"*) wire pkt_sop0,pkt_sop1,pkt_sop2,pkt_sop3,pkt_sop4;
(*mark_debug = "true"*) wire pkt_eop0,pkt_eop1,pkt_eop2,pkt_eop3,pkt_eop4; 
(*mark_debug = "true"*) wire pkt_dval0,pkt_dval1,pkt_dval2,pkt_dval3,pkt_dval4; 
(*mark_debug = "true"*) wire[4:0] pkt_mod0,pkt_mod1,pkt_mod2,pkt_mod3,pkt_mod4; 
(*mark_debug = "true"*) wire[255:0] dout0,dout1,dout2,dout3,dout4; 

wire[8:0] layend0,layend1,layend2,layend3,layend4;
//wire[3:0] pkt_analyser_error_o0,pkt_analyser_error_o1;
wire analyser_is_working_o0,analyser_is_working_o1,analyser_is_working_o2,analyser_is_working_o3,analyser_is_working_o4;
(*mark_debug = "true"*) wire analyser_is_done_o0,analyser_is_done_o1,analyser_is_done_o2,analyser_is_done_o3,analyser_is_done_o4;
wire [0:1023] match_field_0,match_field_1,match_field_2,match_field_3,match_field_4;

reg  [0:1023] match_field_0_r,match_field_1_r,match_field_2_r,match_field_3_r,match_field_4_r;

//wire[209:0] pkt2class0,pkt2class1;
//*********************
//INSTANTCE MODULE
//*********************

receive_contrl U_receive_ctrl (
    .clk(clk), 
    .rst_n(rst_n), 
    .ram_2p_cfg_register(ram_2p_cfg_register),
    .pkt_sop_i(pkt_sop_i), 
    .pkt_eop_i(pkt_eop_i), 
    .pkt_data_i(pkt_data_i), 
    .pkt_dval_i(pkt_dval_i), 
    .pkt_mod_i(pkt_mod_i), 

    .dout0(dout0), 
    .pkt_dval0(pkt_dval0), 
    .pkt_sop0(pkt_sop0), 
    .pkt_eop0(pkt_eop0), 
    .pkt_mod0(pkt_mod0),  

    .dout1(dout1), 
    .pkt_dval1(pkt_dval1), 
    .pkt_sop1(pkt_sop1), 
    .pkt_eop1(pkt_eop1), 
    .pkt_mod1(pkt_mod1),

    .dout2(dout2),
    .pkt_dval2(pkt_dval2),
    .pkt_sop2(pkt_sop2),
    .pkt_eop2(pkt_eop2),
    .pkt_mod2(pkt_mod2),

    .dout3(dout3),
    .pkt_dval3(pkt_dval3),
    .pkt_sop3(pkt_sop3),
    .pkt_eop3(pkt_eop3),
    .pkt_mod3(pkt_mod3),
    
    .dout4(dout4),
    .pkt_dval4(pkt_dval4),
    .pkt_sop4(pkt_sop4),
    .pkt_eop4(pkt_eop4),
    .pkt_mod4(pkt_mod4)
    );
pkt_analysis_ctl U_0 (
    .rst_n(rst_n), 
    .pkt_clk_i(clk), 
    .pkt_sop_i(pkt_sop0), 
    .pkt_eop_i(pkt_eop0), 
    .pkt_data_i(dout0), 
    .pkt_dval_i(pkt_dval0), 
    .pkt_mod_i(pkt_mod0), 
    .pkt_mod_ctl(pkt_mod_ctl),
    .layend(layend0), 
    // .pkt2bv1(pkt2bv1_0),
    // .pkt2bv2(pkt2bv2_0),
    // .pkt2rbve(pkt2rbve_0),
    .match_field(match_field_0),
    //.pkt2class(pkt2class0), 
   // .pkt_analyser_error_o(pkt_analyser_error_o0), 
    .analyser_is_working_o(analyser_is_working_o0), 
    .analyser_is_done_o(analyser_is_done_o0)
    );
pkt_analysis_ctl U_1 (
    .rst_n(rst_n), 
    .pkt_clk_i(clk), 
    .pkt_sop_i(pkt_sop1), 
    .pkt_eop_i(pkt_eop1), 
    .pkt_data_i(dout1), 
    .pkt_dval_i(pkt_dval1), 
    .pkt_mod_i(pkt_mod1), 
    .pkt_mod_ctl(pkt_mod_ctl),
    .layend(layend1), 
    // .pkt2bv1(pkt2bv1_1),
    // .pkt2bv2(pkt2bv2_1),
    // .pkt2rbve(pkt2rbve_1),
    .match_field(match_field_1),
    //.pkt2class(pkt2class1), 
    //.pkt_analyser_error_o(pkt_analyser_error_o1), 
    .analyser_is_working_o(analyser_is_working_o1), 
    .analyser_is_done_o(analyser_is_done_o1)
    );
pkt_analysis_ctl U_2 (
    .rst_n(rst_n), 
    .pkt_clk_i(clk), 
    .pkt_sop_i(pkt_sop2), 
    .pkt_eop_i(pkt_eop2), 
    .pkt_data_i(dout2), 
    .pkt_dval_i(pkt_dval2), 
    .pkt_mod_i(pkt_mod2), 
    .pkt_mod_ctl(pkt_mod_ctl),
    .layend(layend2), 
    // .pkt2bv1(pkt2bv1_0),
    // .pkt2bv2(pkt2bv2_0),
    // .pkt2rbve(pkt2rbve_0),
    .match_field(match_field_2),
    //.pkt2class(pkt2class0), 
   // .pkt_analyser_error_o(pkt_analyser_error_o0), 
    .analyser_is_working_o(analyser_is_working_o2), 
    .analyser_is_done_o(analyser_is_done_o2)
    );
pkt_analysis_ctl U_3 (
    .rst_n(rst_n), 
    .pkt_clk_i(clk), 
    .pkt_sop_i(pkt_sop3), 
    .pkt_eop_i(pkt_eop3), 
    .pkt_data_i(dout3), 
    .pkt_dval_i(pkt_dval3), 
    .pkt_mod_i(pkt_mod3), 
    .pkt_mod_ctl(pkt_mod_ctl),
    .layend(layend3), 
    // .pkt2bv1(pkt2bv1_0),
    // .pkt2bv2(pkt2bv2_0),
    // .pkt2rbve(pkt2rbve_0),
    .match_field(match_field_3),
    //.pkt2class(pkt2class0), 
   // .pkt_analyser_error_o(pkt_analyser_error_o0), 
    .analyser_is_working_o(analyser_is_working_o3), 
    .analyser_is_done_o(analyser_is_done_o3)
    );
pkt_analysis_ctl U_4 (
    .rst_n(rst_n), 
    .pkt_clk_i(clk), 
    .pkt_sop_i(pkt_sop4), 
    .pkt_eop_i(pkt_eop4), 
    .pkt_data_i(dout4), 
    .pkt_dval_i(pkt_dval4), 
    .pkt_mod_i(pkt_mod4), 
    .pkt_mod_ctl(pkt_mod_ctl),
    .layend(layend4), 
    // .pkt2bv1(pkt2bv1_0),
    // .pkt2bv2(pkt2bv2_0),
    // .pkt2rbve(pkt2rbve_0),
    .match_field(match_field_4),
    //.pkt2class(pkt2class0), 
   // .pkt_analyser_error_o(pkt_analyser_error_o0), 
    .analyser_is_working_o(analyser_is_working_o4), 
    .analyser_is_done_o(analyser_is_done_o4)
    );


//*********************
//MAIN CORE
//********************* 


//\u8f6e\u8be2\u5404\u4e2a\u5305\u5206\u6790\u6a21\u5757\uff0c\u8f93\u51fa\u5230\u6d41\u8868\u5339\u914d\u6a21\u5757
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    poll <= 3'd0;
  else
    case(poll)
    3'd0: 
        if(analyser_is_done_o0 || analyser_is_done_r0)
        poll <= 3'd1;
        else 
        poll <= 3'd0;
    3'd1: 
        if(analyser_is_done_o1 || analyser_is_done_r1)
        poll <= 3'd2;
        else 
        poll <= 3'd1;
    3'd2:
        if(analyser_is_done_o2 || analyser_is_done_r2)
        poll <= 3'd3;
        else
        poll <= 3'd2;
    3'd3:
        if(analyser_is_done_o3 || analyser_is_done_r3)
        poll <= 3'd4;
        else
        poll <= 3'd3;
    3'd4:
        if(analyser_is_done_o4 || analyser_is_done_r4)
        poll <= 3'd0;
        else
        poll <= 3'd4;
    default: 
        poll <= 3'd0;
    endcase

/*always@(posedge clk or negedge rst_n)
  if(~rst_n)
    pkt_info <= 210'h0;
  else if(poll == 3'd0 && analyser_is_done_o0)
    pkt_info <=  pkt2class0;
  else if(poll == 3'd0 && analyser_is_done_r0)
    pkt_info <= pkt2class0_r;
  else if(poll == 3'd1 && analyser_is_done_o1)
    pkt_info <=  pkt2class1;
  else if(poll == 3'd1 && analyser_is_done_r1)
    pkt_info <= pkt2class1_r;
  else 
    pkt_info <=  210'h0;*/
// //BV1
// always@(posedge clk or negedge rst_n)
//   if(~rst_n)
//     pkt2bv1 <= 156'h0;
//   else if(poll == 3'd0 && analyser_is_done_o0)
//     pkt2bv1 <= pkt2bv1_0;
//   else if(poll == 3'd0 && analyser_is_done_r0)
//     pkt2bv1 <= pkt2bv1_0_r;
//   else if(poll == 3'd1 && analyser_is_done_o1)
//     pkt2bv1 <= pkt2bv1_1;
//   else if(poll == 3'd1 && analyser_is_done_r1)
//     pkt2bv1 <= pkt2bv1_1_r;
//   else 
//     pkt2bv1 <=  156'h0;
// //BV2
// always@(posedge clk or negedge rst_n)
//   if(~rst_n)
//     pkt2bv2 <= 148'h0;
//   else if(poll == 3'd0 && analyser_is_done_o0)
//     pkt2bv2 <= pkt2bv2_0;
//   else if(poll == 3'd0 && analyser_is_done_r0)
//     pkt2bv2 <= pkt2bv2_0_r;
//   else if(poll == 3'd1 && analyser_is_done_o1)
//     pkt2bv2 <= pkt2bv2_1;
//   else if(poll == 3'd1 && analyser_is_done_r1)
//     pkt2bv2 <= pkt2bv2_1_r;
//   else 
//     pkt2bv2 <=  148'h0;
//1024
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    match_field <= 1024'h0;
  else if(poll == 3'd0 && analyser_is_done_o0)
    match_field <= match_field_0;
  else if(poll == 3'd0 && analyser_is_done_r0)
    match_field <= match_field_0_r;
  else if(poll == 3'd1 && analyser_is_done_o1)
    match_field <= match_field_1;
  else if(poll == 3'd1 && analyser_is_done_r1)
    match_field <= match_field_1_r;
  else if(poll == 3'd2 && analyser_is_done_o2)
      match_field <= match_field_2;
  else if(poll == 3'd2 && analyser_is_done_r2)
    match_field <= match_field_2_r;
  else if(poll == 3'd3 && analyser_is_done_o3)
      match_field <= match_field_3;
  else if(poll == 3'd3 && analyser_is_done_r3)
    match_field <= match_field_3_r;
  else if(poll == 3'd4 && analyser_is_done_o4)
      match_field <= match_field_4;
  else if(poll == 3'd4 && analyser_is_done_r4)
    match_field <= match_field_4_r;
  else 
    match_field <=  1024'h0;
//RBVE
// always@(posedge clk or negedge rst_n)
//   if(~rst_n)
//     pkt2rbve <= 149'h0;
//   else if(poll == 3'd0 && analyser_is_done_o0)
//     pkt2rbve <= pkt2rbve_0;
//   else if(poll == 3'd0 && analyser_is_done_r0)
//     pkt2rbve <= pkt2rbve_0_r;
//   else if(poll == 3'd1 && analyser_is_done_o1)
//     pkt2rbve <= pkt2rbve_1;
//   else if(poll == 3'd1 && analyser_is_done_r1)
//     pkt2rbve <= pkt2rbve_1_r;
//   else 
        // pkt2rbve <=  149'h0;
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    layend <= 9'h0;
  else if(poll == 3'd0 && analyser_is_done_o0)
    layend <=  layend0;
  else if(poll == 3'd0 && analyser_is_done_r0)
    layend <= layend0_r;
  else if(poll == 3'd1 && analyser_is_done_o1)
    layend <=  layend1;
  else if(poll == 3'd1 && analyser_is_done_r1)
    layend <= layend1_r;
  else if(poll == 3'd2 && analyser_is_done_o2)
    layend <=  layend2;
  else if(poll == 3'd2 && analyser_is_done_r2)
    layend <= layend2_r;
  else if(poll == 3'd3 && analyser_is_done_o3)
    layend <=  layend3;
  else if(poll == 3'd3 && analyser_is_done_r3)
    layend <= layend3_r;
  else if(poll == 3'd4 && analyser_is_done_o4)
    layend <=  layend4;
  else if(poll == 3'd4 && analyser_is_done_r4)
    layend <= layend4_r;
  else 
    layend <=  9'h0;

always@(posedge clk or negedge rst_n)
  if(~rst_n)
    analyser_is_done_r0 <= 1'b0;
  else if(analyser_is_done_o0 && poll!=3'd0)
    analyser_is_done_r0 <= 1'b1;
  else if(poll == 3'd0)
    analyser_is_done_r0 <= 1'b0;
  else 
    analyser_is_done_r0 <= analyser_is_done_r0;

always@(posedge clk or negedge rst_n)
  if(~rst_n)
    analyser_is_done_r1 <= 1'b0;
  else if(analyser_is_done_o1 && poll!=3'd1)
    analyser_is_done_r1 <= 1'b1;
  else if(poll == 3'd1)
    analyser_is_done_r1 <= 1'b0;
  else 
    analyser_is_done_r1 <= analyser_is_done_r1;

always@(posedge clk or negedge rst_n)
  if(~rst_n)
    analyser_is_done_r2 <= 1'b0;
  else if(analyser_is_done_o2 && poll!=3'd2)
    analyser_is_done_r2 <= 1'b1;
  else if(poll == 3'd2)
    analyser_is_done_r2 <= 1'b0;
  else 
    analyser_is_done_r2 <= analyser_is_done_r2;

always@(posedge clk or negedge rst_n)
  if(~rst_n)
    analyser_is_done_r3 <= 1'b0;
  else if(analyser_is_done_o3 && poll!=3'd3)
    analyser_is_done_r3 <= 1'b1;
  else if(poll == 3'd3)
    analyser_is_done_r3 <= 3'd0;
  else 
    analyser_is_done_r3 <= analyser_is_done_r3;

always@(posedge clk or negedge rst_n)
  if(~rst_n)
    analyser_is_done_r4 <= 1'b0;
  else if(analyser_is_done_o4 && poll!=3'd4)
    analyser_is_done_r4 <= 1'b1;
  else if(poll == 3'd4)
    analyser_is_done_r4 <= 1'b0;
  else 
    analyser_is_done_r4 <= analyser_is_done_r4;

// always@(posedge clk or negedge rst_n)
//   if(~rst_n)
//     pkt2bv1_0_r <= 156'h0;
//   else if(analyser_is_done_o0 && poll!=3'd0)
//     pkt2bv1_0_r <= pkt2bv1_0;
//   else 
//     pkt2bv1_0_r <= pkt2bv1_0_r;

// always@(posedge clk or negedge rst_n)
//   if(~rst_n)
//     pkt2bv1_1_r <= 9'h0;
//   else if(analyser_is_done_o1 && poll!=3'd1)
//     pkt2bv1_1_r <= pkt2bv1_1;
//   else 
//     pkt2bv1_1_r <= pkt2bv1_1_r;

// always@(posedge clk or negedge rst_n)
//   if(~rst_n)
//     pkt2bv2_0_r <= 148'h0;
//   else if(analyser_is_done_o0 && poll!=3'd0)
//     pkt2bv2_0_r <= pkt2bv2_0;
//   else 
//     pkt2bv2_0_r <= pkt2bv2_0_r;

// always@(posedge clk or negedge rst_n)
//   if(~rst_n)
//     pkt2bv2_1_r <= 148'h0;
//   else if(analyser_is_done_o1 && poll!=3'd1)
//     pkt2bv2_1_r <= pkt2bv2_1;
//   else 
//     pkt2bv2_1_r <= pkt2bv2_1_r;

// always@(posedge clk or negedge rst_n)
//   if(~rst_n)
//     pkt2rbve_0_r <= 149'h0;
//   else if(analyser_is_done_o0 && poll!=3'd0)
//     pkt2rbve_0_r <= pkt2rbve_0;
//   else 
//     pkt2rbve_0_r <= pkt2rbve_0_r;

// always@(posedge clk or negedge rst_n)
//   if(~rst_n)
//     pkt2rbve_1_r <= 149'h0;
//   else if(analyser_is_done_o1 && poll!=3'd1)
//     pkt2rbve_1_r <= pkt2rbve_1;
//   else 
//     pkt2rbve_1_r <= pkt2rbve_1_r;
    
always@(posedge clk or negedge rst_n)
      if(~rst_n)
        match_field_0_r <= 1024'h0;
      else if(analyser_is_done_o0 && poll!=3'd0)
        match_field_0_r <= match_field_0;
      else 
        match_field_0_r <= match_field_0_r;
    
always@(posedge clk or negedge rst_n)
      if(~rst_n)
        match_field_1_r <= 1024'h0;
      else if(analyser_is_done_o1 && poll!=3'd1)
        match_field_1_r <= match_field_1;
      else 
        match_field_1_r <= match_field_1_r;

always@(posedge clk or negedge rst_n)
      if(~rst_n)
        match_field_2_r <= 1024'h0;
      else if(analyser_is_done_o2 && poll!=3'd2)
        match_field_2_r <= match_field_2;
      else 
        match_field_2_r <= match_field_2_r;

always@(posedge clk or negedge rst_n)
      if(~rst_n)
        match_field_3_r <= 1024'h0;
      else if(analyser_is_done_o3 && poll!=3'd3)
        match_field_3_r <= match_field_3;
      else 
        match_field_3_r <= match_field_3_r;

always@(posedge clk or negedge rst_n)
      if(~rst_n)
        match_field_4_r <= 1024'h0;
      else if(analyser_is_done_o4 && poll!=3'd4)
        match_field_4_r <= match_field_4;
      else 
        match_field_4_r <= match_field_4_r;



always@(posedge clk or negedge rst_n)
  if(~rst_n)
    layend0_r <= 9'h0;
  else if(analyser_is_done_o0 && poll!=3'd0)
    layend0_r <= layend0;
  else 
    layend0_r <= layend0_r;
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    layend1_r <= 9'h0;
  else if(analyser_is_done_o1 && poll!=3'd1)
    layend1_r <= layend1;
  else 
    layend1_r <= layend1_r;

always@(posedge clk or negedge rst_n)
  if(~rst_n)
    layend2_r <= 9'h0;
  else if(analyser_is_done_o2 && poll!=3'd2)
    layend2_r <= layend2;
  else 
    layend2_r <= layend2_r;

always@(posedge clk or negedge rst_n)
  if(~rst_n)
    layend3_r <= 9'h0;
  else if(analyser_is_done_o3 && poll!=3'd3)
    layend3_r <= layend3;
  else 
    layend3_r <= layend3_r;

always@(posedge clk or negedge rst_n)
  if(~rst_n)
    layend4_r <= 9'h0;
  else if(analyser_is_done_o4 && poll!=3'd4)
    layend4_r <= layend4;
  else 
    layend4_r <= layend4_r;


always@(posedge clk or negedge rst_n)
  if(~rst_n)
    analyser_is_done_o  <= 1'b0;
  else if(poll == 3'd0 && analyser_is_done_o0)
    analyser_is_done_o  <=  1'b1;
  else if(poll == 3'd0 && analyser_is_done_r0)
    analyser_is_done_o  <= 1'b1;
  else if(poll == 3'd1 && analyser_is_done_o1)
    analyser_is_done_o  <= 1'b1;
  else if(poll == 3'd1 && analyser_is_done_r1)
    analyser_is_done_o  <= 1'b1;
  else if(poll == 3'd2 && analyser_is_done_o2)
    analyser_is_done_o  <= 1'b1;
  else if(poll == 3'd2 && analyser_is_done_r2)
    analyser_is_done_o  <= 1'b1;
  else if(poll == 3'd3 && analyser_is_done_o3)
    analyser_is_done_o  <= 1'b1;
  else if(poll == 3'd3 && analyser_is_done_r3)
    analyser_is_done_o  <= 1'b1;
  else if(poll == 3'd4 && analyser_is_done_o4)
    analyser_is_done_o  <= 1'b1;
  else if(poll == 3'd4 && analyser_is_done_r4)
    analyser_is_done_o  <= 1'b1;
  else 
    analyser_is_done_o  <=  1'b0;

assign analyser_is_working_o = analyser_is_working_o0 | analyser_is_working_o1 | analyser_is_working_o2 | analyser_is_working_o3 | analyser_is_working_o4;
//*********************
endmodule    // hookup byte controller block
    
